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ASIL D IP

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Compare 99 IP from 15 vendors (1 - 10)
  • Single channel ADAS chip with FuSa monitor
    • The SFA 250A has been designed to be easy to adapt to suit the support needs of the customer’s IP as it is scalable, both in terms of function and performance, as well as modular as multiple versions can be combined to form larger solutions.
    Block Diagram -- Single channel ADAS chip with FuSa monitor
  • ABX® Automotive Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
    • Integrated adaptive body bias (ABB) control loop
    • Charge pumps for N-Well and P-Well voltages, operated from IO supply voltage level
    Block Diagram -- ABX® Automotive Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
  • ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Memory Compiler in TSMC (16nm,22nm,28nm,40nm,55nm,90BCD+,110nm,152nm,180BCD)
    • Synchronous read/write operation
    • Low leakage current and lower operation power consumption
    • Minimum metal layer requirement: 4/3 metal layers
    • High density layout structure and small area design
  • IP for Automotive Applications
    • M31 M-PHY certified by ISO 26262 ASIL-B is a serial interface technology which is widely adopted in automotive devices interface transmission. As a MIPI Alliance contributor and an Interface IP provider, M31 provides a silicon-proven, low-power and low cost M-PHY IP in different process nodes.
    • M31 D-PHY certified by ISO 26262 ASIL-B Ready is a very popular physical layer interface for mobile applications as it is a flexible, high-speed, low-power and low-cost solution. M31 also provides silicon-proven D-PHY in various process nodes. Many car and mobile devices manufacturers are adopting MIPI specifications because the solutions are mature, relatively simple to use.
    • M31 PCIe PHY certified by ISO 26262 ASIL-B Ready provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. It is optimized the minimal die area and low power consumption. The safe mechanism of PCIe PHY is compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base It can meet the complete range of PCIe high bandwidth application in different channel conditions.
    • M31 High Speed Memory Compilers including “One-Port”, “Two-Port”, “Single-Port”, and “Dual-Port” have all passed ISO 26262 ASIL-B Ready and ASIL-D Ready certification. High speed SRAM instances are the fundamental blocks for all automotive applications. Users can generate different memory types, sizes and configurations according to different requirements. In addition, the compilers provide customers comprehensive product applications with vehicle safety requirements. Furthermore, the whole series products are ASIL D Ready certified and provide optimized IP portfolio solutions for different customer’ designs with more flexible choices of design architecture.
  • Ncore 3 Coherent Network-on-Chip (NoC)
    • Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
    • AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
    • Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
    • Configurable last-level caches
    Block Diagram -- Ncore 3 Coherent Network-on-Chip (NoC)
  • CodaCache® Last Level Cache IP
    • Standalone IP
    • 1.2 GHz frequency in 16FF+TT process
    • Protocol interoperability: AMBA AXI 4
    Block Diagram -- CodaCache® Last Level Cache IP
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