ASIL D IP
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ARC HS48FSx4 quad-core, host processor , ASIL B / ASIL D support, incl. lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC HS48FS, host processor, with ASIL B / ASIL D support, including lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC HS47DFSx4 quad-core, w/ DSP extensions, ASIL B / ASIL D support, incl. lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC HS47DFS, with DSP extensions, and ASIL B / ASIL D support, including lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC HS46FSx4 quad-core with ASIL B / ASIL D support, including lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC HS46FS with ASIL B / ASIL D support, including lock-step for functional safety applications
- Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
- Certified for ISO 262626 safety and ISO/SAE 21434 cybersecurity compliance
- Single solution for Automotive Safety Integrity Level B, C and D (ASIL B, C, D); Supports both ASIL D lockstep operation or ASIL B, C single core operation
- Includes hardware safety features: ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
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ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive SoC development and accelerate ISO 26262 qualification
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
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FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- ARM® Cortex®-R5 and Cortex-R7 processor port checking
- Hardware duplication and redundancy
- Custom ECC and parity generation and checking
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8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
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ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
- Compliant with PCI Express IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP packet-based interface
- Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
