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ARM Cortex-M0 IP

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  • Arm Cortex-M0+
    • Memory protection unit - Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
    • Binary upward compatible with all other Cortex-M processors - The Cortex-M0+ has mainly 16bit Thumb-2 instructions and few 32bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written for the Cortex-M0+ will run as is on the other processors.
    • Built-in low-power features - Sleep, deep sleep and state retention are three low power modes available to the user.
    • Optional Debug Access Port and Serial Wire Debug - For devices where every pin counts the serial wire debug port uses only two pins.
    Block Diagram -- Arm Cortex-M0+
  • Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
    • Exceptional code density - on average, the mix between 16-bit and 32-bit instructions yields a better code density when compared to 8-bit and 16-bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
    • Binary upward compatible with all other Cortex-M processors - the Cortex-M0 has mainly 16-bit Thumb-2 instructions and few 32-bit ones. These instructions are also present on all the other Cortex-M processors. Hence all code written for the Cortex-M0 will run as is on the other processors.
    • Built-in low-power features - sleep, deep sleep and state retention are three low power modes available to the user
    • Optional Debug Access Port and Serial Wire Debug - for devices where every pin counts the serial wire debug port uses only two pins
    Block Diagram -- Small, Low Power, Energy Efficient 32-bit Microcontroller Processor
  • ComputeRAM
    • Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
    • Low power sleep mode with data retention
    • Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
    • Bit-accurate computation
    Block Diagram -- ComputeRAM
  • Block Diagram -- SecurCore_SC000
  • AHB Subsystem
    • Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as: BA2x, ARM Cortex-M0/M1M3/M4, and Several RISC-V processors
    • AHB-SBS-BASE integrates: AHB Multi-Layer Interconnect, xSPI Controller, SRAM Controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
    • AHB-SBS-EXT adds: Multichannel DMA, SPI-to-AHB bridge, and External parallel flash or SRAM controller
    • Highly configurable and customizable
    Block Diagram -- AHB Subsystem
  • APB Subsystem
    • AMBA® APB Bridge and Peripherals for rapid integration with processors like: BA2x, ARM Cortex-M0/M1M3/M4, and several RISC-V processors
    • AHB or AXI to APB Bridge
    • 2C Master/Slave
    • Single, Dual, Quad and Octal SPI Master/Slave
    Block Diagram -- APB Subsystem
  • AHB Performance Subsystem - ARM M0
    • Supports Cortex-M0 (or equivalent) processor
    • AMBA® 2.0 (AHB)
    • AHB Multi-matrix bus infrastructure
    • External Nor Flash controller
    Block Diagram -- AHB Performance Subsystem - ARM M0
  • AHB Low Power Subsystem - ARM M0
    • Supports Cortex-M0 (or equivalent) processor.
    • Power Management Unit
    • AMBA® 3.0 (AHBLite)
    Block Diagram -- AHB Low Power Subsystem - ARM M0
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