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ARC IoT IP

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Compare 9 IP from 2 vendors (1 - 9)
  • ARC IoT Communications IP Subsystem
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM11D processor with DSP extensions delivers extremely low gate count and highly efficient processing performance
    • Hardware accelerators for key communications functions such as Viterbi decoding dramatically reduce cycle counts and energy consumption
    • Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs
    Block Diagram -- ARC IoT Communications IP Subsystem
  • ARC EM6 32-bit processor core with cache for embedded applications
    • Very small size - 0.01mm2 (28 HPM)
    • 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
    • Up to 240 interrupts with 16 levels
    • 512B - 2MB instruction closely coupled memory (ICCM)
    Block Diagram -- ARC EM6 32-bit processor core with cache for embedded applications
  • ARC EM4 32-bit processor core, ARC V2 ISA, for embedded applications
    • Very small size - 0.01mm2 (28 HPM)
    • 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
    • Up to 240 interrupts with 16 levels
    • 512B - 2MB instruction closely coupled memory (ICCM)
    Block Diagram -- ARC EM4 32-bit processor core, ARC V2 ISA, for embedded applications
  • ARC Data Fusion Voice/Speech Option
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
    • Extensive library of software DSP functions enable sensor signal processing
    • Hardware accelerators boost performance efficiency and reduce power consumption
    Block Diagram -- ARC Data Fusion Voice/Speech Option
  • ARC VPX DSPs are VLIW/SIMD processors optimized for highly parallel processing with minimal energy and area consumption for a range of embedded workloads
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Narrow band - IoT Release-14 e-NodeB PHY. (L1) IP
    • 3GPP Rel-14 Cat-NB UE Solution
    • FDD Support
    • Single Antenna Tx and Rx
    • 200 KHz Bandwidth
  • Data Fusion IP Subsystem
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
    • Extensive library of software DSP functions enable sensor signal processing
    • Hardware accelerators boost performance efficiency and reduce power consumption
    Block Diagram -- Data Fusion IP Subsystem
  • Sensor & Control IP Subsystem
    • Integrated, pre-verified hardware and software IP subsystem consisting of a choice of an ARC EM4 or EM6 processor, serial digital interfaces, data converter interfaces, hardware accelerators, software library of DSP functions and I/O drivers
    • Optional IEEE 754-2008 compliant FPU reduces energy consumption by 10X for sensor applications executing floating point operations
    • Integrated hardware accelerators for sensor-specific functions boost performance efficiency and reduce power consumption by up to 85% compared to discrete solutions
    • Highly configurable with tightly integrated peripherals and dedicated hardware maximize sensor processing efficiency
    Block Diagram -- Sensor & Control IP Subsystem
  • ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
    • 32-bit RISC-V embedded CPU with a 5-stage pipeline
    • DSP implementation to extend the RISC-V baseline (RMX-500D)
    • 2 KB to 64 KB instruction & data L1 caches
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