Ahb IP

The core implements the exponentiation operation of the RSA cryptography Q = Pk.
The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
Once the operation is complete, the result Q can be read through the AHB interface.

The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.
The core is compatible with the Philips I²C standard.

The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.

The AHB Verification IP provides a complete solution for Verification of AMBA 3.0 AHB-Lite protocol v1.0 component of a SOC or ASIC
The AHB-Lite Verification IP is fully compliant with standard AMBA 3 AHB-Lite Specification
AMBA 3.0 AHB-Lite VIP is supported natively in SystemVerilog and UVM

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
It is expected that the AXI clock and the AHB clock are derived from the same clock source, and that the period of the AHB Lite clock is an integer multiple of the AXI clock in the range [1,16].

The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
The AHB SRAM Controller provides zero-wait-state AHB access to the synchronous SRAM in all cases except for the following back-toback events: an AHB write directly followed by an AHB read.

The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards Publication 197 (FIPS 197).
The AES IP Core implements the Rijndael algorithm which is a symmetric block cipher that can process 128-bit data blocks using 128, 192, or 256-bit cipher keys.

The AMBA AHB Verification IP validates system-level communication and functionality in SoCs using the AHB protocol. It supports single-cycle transfers, burst operations, and split transactions, ensuring high-speed data transfers between components.
This VIP is ideal for debugging, performance optimization, and ensuring reliability in diverse SoC architectures. It supports master, slave, and bus interconnect simulations, making it essential for complex designs in industries like automotive and IoT.

Compliant to AMBA®5 AHB Protocol specifications and AMBA 3 AHB-Lite Verification IP from ARM
Support for all type of AMBA AHB devices:
- AHB5Master
- AHB5Slave
AHB5Master
AHB5Slave

AHB IP