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64 Bit CPU IP

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Compare 19 IP from 13 vendors (1 - 10)
  • High-performance 32-bit RISC CPU
    • 32-bit RISC architecture
    • 16 or 32 general purpose registers
    • 104 basic instructions and 10 addressing modes
    Block Diagram -- High-performance 32-bit RISC CPU
  • Compact, low-power 32-bit RISC CPU
    • 32-bit RISC architecture
    • 16 or 32 general purpose registers
    • 104 basic instructions and 10 addressing modes
    • Optional IEEE 754 floating point unit (FPU)
    Block Diagram -- Compact, low-power 32-bit RISC CPU
  • UART with FIFOs, IrDA and Synchronous CPU Interface
    • Capable of running all existing 16450 and 16550a software
    • Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
    • In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU
    • Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
    Block Diagram -- UART with FIFOs, IrDA and Synchronous CPU Interface
  • Radio over Ethernet (RoE)
    • Complies with IEEE 1914.3 standard
    • Supports multiple streams of CPRI and Ethernet
    • Complies with CPRI 7.0 standard
    Block Diagram -- Radio over Ethernet (RoE)
  • CAN 2.0 & CAN FD Bus Controller IP
    • Conforms to Bosch CAN 2.0B Active
    • 8/16/32-bit CPU slave interface with little or big endianess
    • Simple interface allows easy connection to CPU
    • Data rate up to 1 Mbps
    Block Diagram -- CAN 2.0 & CAN FD Bus Controller IP
  • Configurable CAN Bus Controller
    • Conforms to Bosch CAN 2.0B Active
    • 8/16/32-bit CPU slave interface with small or big endianness
    • Simple interface allows easy connection to CPU
    • Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
  • Block Diagram -- General Purpose & Bridge DMA
  • 100G MAC/PCS Ultra Ethernet
    • The IP integrates MAC Layer, RS Sub-Layer and 100G PCS Base-R cores according to IEEE 802.3 standard to provide seamless connection between an application and serdes interfaces
    • 128-bit interface for TX and RX between MAC and the application Serdes interface – configurable to support PAM2 and PAM 4
    Block Diagram -- 100G MAC/PCS Ultra Ethernet
  • Time Triggered Controller Area Network IP
    • Support of Classical CAN and CAN FD up to 64 byte according ISO 11898-1:2015
    • TTCAN protocol level 1 and level 2 completely in hardware
    • Event synchronized time-triggered comm. supported
    • CAN Error Logging
    Block Diagram -- Time Triggered Controller Area Network IP
  • Configurable CAN Bus Controller IP with Flexible Data-Rate
    • Designed in accordance to ISO 11898-1:2015
    • Supports CAN 2.0B and CAN FD frames
    • Support up to 64 bytes data frames
    • Flexible data-rates supported
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