IP Catalog > 40 Gbps TCP Endpoint

40 Gbps TCP Endpoint IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (115)
Compare 115 IP from 23 vendors (1 - 10)
  • 40 Gbps ODU Multiplexer
    • The TPOC ODU MUXs are specifically designed for large Tbps OTN Packet-Optical Transport Systems with connectivity for hundreds of ODU0/1/2/3/4/flex.
    • The TPOC314 is a cost-efficient 40 Gbps ODU multiplexer that multiplexes/demultiplexes an OTU3 to any mix of ODU0/1/2/3/flex containers.
    • The ODUk channels are segmented into fixed-size cells by the built-in SAR function and sent over Interlaken interface for switching in a switch fabric.
  • PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
    • Fully compliant with PCI Express Base 5.0 electrical specifications
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
    Block Diagram -- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
  • Ultra-Compact 3GPP Cipher Core
    • Keystream generation using the ZUC Algorithm version 1.6 (ZUC-2011)
    • High throughput: up to 40 Gbps in 65 nm process, 10 Gbps in Altera Stratix III
    • Small size: from 7.5K ASIC gates
    • Satisfies ETSI SAGE ZUC and EAE3/EIA3 specifications
    Block Diagram -- Ultra-Compact 3GPP Cipher Core
  • PCIe Gen5/CXL combo PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
    • Fully compliant with PCI Express Base 5.0 electrical specification
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE5.2 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen5/CXL combo PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
  • PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
    • Fully compliant with PCI Express Base 5.0 electrical specification
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE5.2 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
  • SFI-5
    • The SFI-5 core is fully compliant with the Optical Internetworking Forum (OIF) Implementation Agreement OIF-SFI5-01.02
    • Data path uses 17 SERDES transceivers operating in 8-bit only mode
    • Sixteen 16-bit wide internal receive and transmit data paths
    • Supported through ispLEVER IPexpress for easy user configuration and parameterization
    Block Diagram -- SFI-5
  • GDDR7 Memory Controller
    • Up to 40 Gbps per pin operation
    • Optimized for high efficiency and low latency across a wide variety of traffic scenarios
  • USB4 Controller & Router IP
    • Lowest risk: Based on USB 3.2 controller that is proven in multiple designs
    • Lowest power: Reduce power consumption with USB power saving modes, Uniform Power Format, and hibernation option with dual power rails
    • Flexible data buffering options to optimize performance vs area
    • Supports all USB speed modes
  • USB4 PHY in Samsung (SF4X)
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
  • USB4 PHY in TSMC (N7, N6, N5, N3E)
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
×
Semiconductor IP