32-bit DSP IP
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103
IP
from 22 vendors
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10)
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ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC EM7D DSP Enhanced 32-bit processor core with caches, ARCv2DSP ISA, for low power embedded DSP ap
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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Highest code density, Low Power 32-bit Processor with optional DSP
- High Performance 32-bit CPU/DSP
- Power Management Unit
- Advanced Debug Unit
- Integrated Tick Timer
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Compact High-Speed 32-bit CPU Core with DSP
- AndeStar™ V5 ISA, compliant to RISC-V technology
- DSP/SIMD ISA to boost the performance of digital signal processing
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ARC HS47D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions and I&D cache
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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ARC HS45D 32-bit, dual-issue processor core, ARCv2DSP ISA, with 100+ DSP instructions for embedded applications
- Combination Dual-issue, 32-bit RISC + DSP processor
- Delivers up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
- ARCv2DSP ISA adds over 150 DSP instructions
- Easy DSP programming support with Metaware C/C++ Compiler
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ARC EM5D Enhanced 32-bit processor core, ARCv2DSP ISA, for low power embedded DSP applications
- Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
- Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
- RAM configuration optimized for efficient area and power
- Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
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32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
- CPU Core
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ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D
- D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
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512-bit Vector DSP IP, Single Core with Functional Safety
- Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
- Four-way VLIW architecture combining scalar and vector operations
- 128-bit, 256-bit and 512-bit vector lengths
- 8, 16, and 32-bit integer SIMD engines
