Highest code density, Low Power 32-bit Processor with optional DSP

Overview

Key Features

• High Performance 32-bit CPU/DSP
  • 32-bit architecture implementing Beyond BA2 Instruction Set
  • Single-cycle instruction execution on most instructions
  • Fast and precise internal interrupt response
  • Thirty-two, 32-bit general-purpose registers
  • Custom user instructions
  • 1.36 DMIPS / MHz
• Power Management Unit
  • Power reduction from 2x to 100x
  • Software controlled clock frequency in slow and idle modes
  • Interrupt wake-up in doze and sleep modes
  • Dynamic clock gating for individual units
• Advanced Debug Unit
  • Conventional target-debug agent with a debug exception handler
  • Non-intrusive debug/trace for both RISC and system
  • Access and control of debug unit from RISC or via development interface
  • Complex chained watchpoint and breakpoint conditions
• Integrated Tick Timer
  • Task scheduling and precise time measuring
  • Maximum timer range of 2^32 clock cycles
  • Maskable tick-timer interrupt
  • Single-run, restartable or continuous mode
• Programmable Interrupt Controller
  • 32 maskable interrupt sources

Benefits

• Dense code: Highest code density in the industry means less on-chip memory
• Efficient: 1.36DMIPs/MHz
• Configurable: allows optimal implementation
• Small: reduces die size, power consumption
• Proven: Volume production proven core
• Frugal: Excellent power control increases battery life
• Easy: robust, industry standard development tool chain including debugger, simulator etc. for Windows and Linux.

Block Diagram

Applications

• Internet, networking and telecom
• Embedded
• Portable and wireless
• Home entertainment consumer electronics
• Automotive

Deliverables

• Verilog RTL source code
• Test bench in Verilog
• Silicon Proven Reference SOC/ASIC design
• Software development tools for Windows and Linux
• Operating systems and Board Support Package
• Evaluation board with silicon SOC/ASIC, running Linux
• Engineering support

Technical Specifications