2D/2.5D Graphics Engine IP
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46
IP
from 19 vendors
(1
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10)
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2D Graphics Hardware Accelerator (AXI4 Bus)
- Bit Block Transfer - 3 Independent Memory Sources of data
- .2D Raster Operations (ROP) performed on Block Transfers
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Advanced 2D Graphics Contoller
- Fully synchronous, synthesizable and technology independent RTL code
- Capable of drawing shapes such as pixels, lines and rectangles
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2D Blit and Raster Graphics
- All buffer formats 100% compatible
- Flexible pixel formats (1/2/4/8/16/18/24/32 bpp; any bit width per channel)
- YUV support (packed, planar, 4:4:4, 4:2:2, 4:2:0, progressive, interlaced)
- Dynamic re-configuration of processing units
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Programmable Clock Generator
- Easily solve different clocking schemes in Xilinx device and adopt clocking during the SoC operation
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Display controller for dual-display
- Scan directions: 90/180/270° rotation, horizontal/vertical flip
- Multiple layers (alpha blend) with configurable mapping
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Camera capture unit for multi-camera systems
- Down-scaling
- De-interlacing
- Histogram measurement
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PNG Lossless Compression Encoder
- Efficient PNG Encoder
- Easy to Use and Integrate
- Throughput & Latency
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PNG Lossless Compression Decoder
- Compliant with the ISO/IEC 15948 and RFC 2083 standards
- All chunk types
- All color types
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2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- Vertically integrated HW + SW solution
- Monolithique HW building block, open to any system integration. Can be associated with any companion IP:
- 2 hardware versions:
- Software ported on numerous processors and OS
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High-performance 2D (sprite graphics) GPU IP combining high pixel processing capacity and minimum gate count.
- Pixel performance
- Texture size
- Color format
- 2D rendering