IP Catalog > 25G Ethernet

25G Ethernet IP

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Compare 57 IP from 13 vendors (1 - 10)
  • 25G Ethernet MAC and PCS + RS-FEC
    • Compliant with IEEE802.3by-2016 and 25/50G Ethernet Consortium
    • Ethernet MAC supports 25GbE line rate with flexible feature set
    • Soft PCS logic interfacing to standard serial transceiver at 25.78125Gbps
    • MAC FEATURES
    Block Diagram -- 25G Ethernet MAC and PCS + RS-FEC
  • 25G Ethernet PHY in TSMC (16nm, 12nm, N7)
    • Includes one, two or four full-duplex transceivers (transmit and receive functions)
    • Supports back channel initialization, aggregation, bifurcation, and power management
    • Supports both internal and external reference clock connections to the PHY
    • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • 25G Ethernet PHY in GF (14nm)
    • Includes one, two or four full-duplex transceivers (transmit and receive functions)
    • Supports back channel initialization, aggregation, bifurcation, and power management
    • Supports both internal and external reference clock connections to the PHY
    • Configurable transmitter and receiver equalization, supporting chip-to-chip, port side, backplane interfaces
  • ETHERNET 25G PCS IP
    • Supports IEEE Standard 802.3.2018 Clause 107
    • Supports 25G Base R
    • Supports 25G Base KR
    • Supports 64b/66b encoding and decoding for transmit and receive path
  • ETHERNET 25G MAC IP
    • Compliant with IEEE Standard 802.3-2018 specification
    • Supports full duplex mode of operation
    • Supports Standard 25Gbps Ethernet link layer data
    • Supports 25GMII(Clause 106) interface operating at 390.625MHz
  • ETHERNET 25G TSN MAC IP
    • Compliant with IEEE Standard 802.3-2018 Specification - Clause 106
    • Supports Preemption as per IEEE Standard 802.1Qbu and IEEE Standard 802.3br Interspersing Express Traffic
    • Supports timing synchronization as per IEEE Standard 802.1 AS
    • Supports Traffic Scheduling - IEEE Standard 802.1Qbv(Enhancement for Scheduled Traffic) and IEEE Standard 802.1Qav (Credit Based Shaping)
  • 25G IEEE 802.3by Reed-Solomon Forward Error Correction
    • Run-time switchable between IEEE802.3by and 25G Ethernet Consortium Schedule 3 specification mode
    • Low latency
    • Accessible as integrated feature in the 25G Ethernet Subsystem
    • Configuration and status bus
  • 25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 7FF x4 North/South (vertical) poly orientation
  • 25G MR Ethernet PHY, TSMC 7FF x2 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 7FF x2 North/South (vertical) poly orientation
  • 25G MR Ethernet PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
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