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16G SerDes UMC 28HPC+ IP

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Compare 11 IP from 3 vendors (1 - 10)
  • 16G SerDes in 28nm
    • ? Configurable data rate up to 16Gbps
    • ? Multiple 8 lanes transceiver
    • ? Internal high performance Frac-N PLL, support SSC
    • ? 32bit parallel data bus
  • 16G Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x38
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x38
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Ethernet SerDes PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x40
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Ethernet SerDes PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x40
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps
    • Transceiver version including both receiver and transmitter
    • Transmitter only version
    • 40bit/32bit/20bit/16bit selectable parallel data bus
  • GDDR6 PHY for Samsung
    • Derived from Cadence’s silicon-proven DDR, LPDDR, and high-speed SerDes designs
    • Highest data rates with detailed system guidelines
    Block Diagram -- GDDR6 PHY for Samsung
  • GDDR6 PHY for TSMC
    • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
    • Memory controller interface uses DFI 5.0-like standard with extensions for GDDR6
    • Internal and external datapath loop-back modes
    • Per-bit DFE, CTLE, and FFE equalization
  • PCIe 4/3/2 SerDes PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
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