IP Catalog > 100 Gigabit Ethernet

100 Gigabit Ethernet IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (15)
Compare 15 IP from 10 vendors (1 - 10)
  • Gigabit Ethernet Media Access
    • The GEMAC (Gigabit Ethernet Media Access Controller) core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification.
    • The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface.
    • The core can be used in various integrated applications. A single channel MAC with PCI controller would provide an ideal solution for inexpensive NIC cards.
    Block Diagram -- Gigabit Ethernet Media Access
  • Ethernet Device Driver
    • The 802.3 Ethernet Device Driver is developed to support both the 10/ 100 Ethernet IP as well as its Gigabit Ethernet IP.
    • The device driver provides communications between the MAC (Medium Access Control) and the OS (Operating System) as well as access to the overlying network layer protocol and the applications layer.
    Block Diagram -- Ethernet Device Driver
  • 10/100/1000 Ethernet MAC DO-254 IP Core
    • The 10/100/1000 Ethernet MAC Controller DO-254 IP Core implements the Media Access Control as specified in the IEEE 802.3-2008 specification.
    • The Ethernet MAC Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. 
    Block Diagram -- 10/100/1000 Ethernet MAC DO-254 IP Core
  • Flexibilis Redundant Switch - 3 to 8 Port Ethernet IP with HSR/PRP
    • Provides seamless redundant communication for critical traffic
    • Open, interoperable solution supporting HSR, PRP and IEEE 1588 PTP standards
  • Low-Latency 10/100/1000 Ethernet MAC
    • The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
    • Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.  
    Block Diagram -- Low-Latency 10/100/1000 Ethernet MAC
  • UltraScale+ Integrated 100G Ethernet Subsystem
    • Optional built-in 100G RS-FEC
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • Requires license key available at no charge
    • 1588 1-step and 2-step hardware time stamping  
  • UltraScale Integrated 100G Ethernet Subsystem
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • No charge 100G Ethernet MAC and PCS license key enabled
    • Optional fee based soft 100G RS-FEC for UltraScale FPGAs
    • 1588 1-step and 2-step hardware time stamping  
  • UltraScale Integrated 100G Ethernet MAC/PCS
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • No charge license key enabled
    • 1588 1-step and 2-step hardware time stamping  
    • Allows insertion of custom logic such as RS-FEC between the 100G Ethernet integrated block and GT
  • Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
    • Designed to IEEE 802.3-2012 specification
    • Full-duplex operation
    • Supports speeds up to 2.5 Gigabit per second
    • Supports Select I/O or Transceiver implementations
  • MAC 10/100/1000 Ethernet Controller
    • IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
    • Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
    • Supports full- and half-duplex operation (selectable via a core configuration registers)
    • CSMA/CD protocol for half-duplex operation
    Block Diagram -- MAC 10/100/1000 Ethernet Controller
×
Semiconductor IP