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100 Gigabit Ethernet IP

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Compare 14 IP from 9 vendors (1 - 10)
  • Gigabit Ethernet Media Access
    • Highly Integrated Gigabit Ethernet Media Access Controller (MAC) core
    • Compliance with IEEE 802.3-2000 specifications
    • Backward Compatible with 100/10 Mbits.
    • Network data bandwidth: 1 Gbps in CSMA/CD (Half Duplex) and 2 Gbps in Full Duplex.
  • DO-254 10/100/1000 Ethernet MAC
    • Configurable bit rate (1000 Mb/s, 100 Mb/s or 10 Mb/s)
    • DAL A according to DO-254 / ED-80
    • Compliant to the following clauses of the IEEE 802.3-2008 specification:
    • Compliant to the RMII specification (March 20, 1998)
    Block Diagram -- DO-254 10/100/1000 Ethernet MAC
  • Flexibilis Redundant Switch - 3 to 8 Port Ethernet IP with HSR/PRP
    • Provides seamless redundant communication for critical traffic
    • Open, interoperable solution supporting HSR, PRP and IEEE 1588 PTP standards
  • Serial Gigabit Media Independent Interface
    • Offers a reduced pin-count interface between MII or GMII Ethernet MACs and Physical Layer devices
    • Supports Revision 1.7 of the Serial GMII specification
    • Supports MII 10/100 Mbps and GMII 1000 Mbps Ethernet speeds
    • Supports Full Duplex transfers at all speeds, and Half Duplex at 10/100Mbps
  • Low-Latency 10/100/1000 Ethernet MAC
    • The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications.
    • Featuring extremely low egress and ingress latency, the core is ideal for the implementation of TSN Ethernet nodes, live streaming and other devices requiring minimum latency in the reception and transition of Ethernet frames.  
    Block Diagram -- Low-Latency 10/100/1000 Ethernet MAC
  • UltraScale+ Integrated 100G Ethernet Subsystem
    • Optional built-in 100G RS-FEC
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • Requires license key available at no charge
    • 1588 1-step and 2-step hardware time stamping  
  • UltraScale Integrated 100G Ethernet Subsystem
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • No charge 100G Ethernet MAC and PCS license key enabled
    • Optional fee based soft 100G RS-FEC for UltraScale FPGAs
    • 1588 1-step and 2-step hardware time stamping  
  • UltraScale Integrated 100G Ethernet MAC/PCS
    • Supports 10 lanes x10.3125 CAUI-10, 4 lanes x25.78125G  CAUI-4 or dynamically switchable CAUI-4 and CAUI-10 mode
    • No charge license key enabled
    • 1588 1-step and 2-step hardware time stamping  
    • Allows insertion of custom logic such as RS-FEC between the 100G Ethernet integrated block and GT
  • Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII
    • Designed to IEEE 802.3-2012 specification
    • Full-duplex operation
    • Supports speeds up to 2.5 Gigabit per second
    • Supports Select I/O or Transceiver implementations
  • MAC 10/100/1000 Ethernet Controller
    • IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
    • Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
    • Supports full- and half-duplex operation (selectable via a core configuration registers)
    • CSMA/CD protocol for half-duplex operation
    Block Diagram -- MAC 10/100/1000 Ethernet Controller
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