Video Frame buffer permits an asynchronous video source to be buffered in an external memory. Features a generic memory interface suitable for all memory types including SDRAM, DDR2, DDR3 etc. Ideal for adapting to different pixel rates and frame rates. Scalable architecture allows multiple video inputs to be synchronized together. Can also work as a Genlock with minor modifications.
Video Frame Buffer
Overview
Key Features
- Asynchronous video input
- Output video synchronized to the system clock
- Simple user interface looks like a FIFO
- Supports all standard and any custom video resolution
- Support for 16, 24 or 32-bits per pixel
- Support for 4:2:2 YCbCr, 4:4:4 YCbCr, 24-bit RGB etc.
- Supports frame skip and frame repeat
- Programmable memory burst size
- System diagnostics to monitor performance
- Single 128-bit R/W port to external memory
- Support for 64, 32 or 16-bit R/W port on request
- Optimized for all synchronous memory types
- Fully scalable architecture for any number of video inputs
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All
Availability
Immediate
Related IPs
- Video Frame Buffer
- Video Frame Buffer Read and Video Frame Buffer Write
- AVC/H.264 Video Encoder with Compressed Frame Store
- Video Design Framework for Multi-camera Vision Applications
- SSTL2 Buffer (Vcc=2.5V,Vcore=1.25V, Freq=800Mbps)
- HSTL Buffer (Vcc/Vdd=3.3V/1.8V,Vref=0.75V, Input Swing:0.65~0.85V, Freq=600Mbps)