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ONFI IP

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The ONFI IP cores are used to access the external NAND flash for high speed transactions of multiple pages of read or write data taking advantage of the pipeline performance of newer enterprise NAND flash devices.

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Search (44)
Compare 44 ONFI IP from 11 vendors (1 - 10)
  • ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
    • ONFI v5.0 compliant + Up to 2.4GByte/s.
    • All I/O modes implemented + SDR + NV-DDR + NV-DDR2/3 + NV-LPDDR4
    • Wide hardware support + Four 8-bit data paths + 8 NAND targets each + Data bus inversion.
    • Full PLL support + PLL within PHY + 10MHz SDR + 1.2GHz NV-LPDDR4 + Everything in between
    Block Diagram -- ONFI 5.0 NAND FLASH Controller Compliant to JEDEC
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
  • ONFI 4.0 NAND Flash Controller & PHY
    • • Support ONFI 4.0, EZ – NAND, Standard ClearNAND, Advanced ClearNAND
    • • Support standard asynchronous NAND flash
    • • High performance from 40MT/s to 800MT/s
    • • High density NAND flash up to 1024 Gb
    Block Diagram -- ONFI 4.0 NAND Flash Controller & PHY
  • ONFI 3.2 NAND Flash Controller
    • Compliant to ONFI revision 3.2 standard 
    • Supports NV-DDR2 mode of operation supporting up to 200MHz
    • Supports NV-DDR mode of operation supporting up to 100MHz 
    • Supports legacy Asynchronous devices operating from 10MHz to 50MHz 
    Block Diagram -- ONFI 3.2 NAND Flash Controller
  • Open Nand Flash Interface (ONFI)
    • Compliant with ONFI 2.3/3.0/4.0/4.1/5.0 specifications.
    • Supports Source Synchronous and Asynchronous data interfaces.
    • Supports all mandatory and optional commands.
    • Supports 16 bit bus width operations.
    Block Diagram -- Open Nand Flash Interface (ONFI)
  • ONFI 5.0 Verification IP
    • Compliant to ONFI-2.3 ,ONFI-3.0 ,ONFI-4.0 ,ONFI-4.1 , ONFI-4.2 and ONFI-5.0 specifications.
    • Supports all mandatory and optional commands. Supports generation of Vendor Specific Commands.
    • Supports up to 16-bit bus width operations.
    • Supports implicit and explicit training (DCC, Read DQ, Write DQ Tx, Write DQ Rx).
    Block Diagram -- ONFI 5.0 Verification IP
  • ONFI 5.1 PHY IP
    • Compliant with ONFI 5.1 specification
    • Supports NV-DDR3/NV-LPDDR4, with a maximum rate up to 3600MT/s
    • Supports matched or unmatched DQS
    • Supports WDCA/Per-Pin VREFQ Training for NAND devices
    Block Diagram -- ONFI 5.1 PHY IP
  • 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
    • Supports Both NV-DDR3 and NV-LPDDR4 with 4-tap DFEs
    • Support Decision Feedback Equalization (DFE): For extra high loading, DFE can reduce errors and improve data integrity
    • Compliant with JEDEC 6.0 (TBD) and JESD 230G specifications
    • Supports real-time PVT data-eye monitoring
    Block Diagram -- 4800 ONFI NV-DDR3 and NV-LPDDR4 with 4-tap DFE
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