IP Catalog > Interface IP > Interconnect IP > USB IP > USB 3.0 IP > USB 3.0 PHY IP

USB 3.0 PHY IP

Welcome to the ultimate USB 3.0 PHY IP hub! Explore our vast directory of USB 3.0 PHY IP
All offers in USB 3.0 PHY IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (75)
Compare 75 USB 3.0 PHY IP from 15 vendors (1 - 10)
  • MIPI M-PHY Designed For GF 28nm
    • •Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY Designed For GF 28nm
  • USB 3.0 SSIC PHY
    • Compliant with SSIC specification 1.0
    • Compliant with MIPI-MPHY (Type-1) specification Rev 3.0-r.03
    Block Diagram -- USB 3.0 SSIC PHY
  • USB HSIC PHY - High Speed Inter-Chip IP Core
    • High-Speed 480Mbps data rate only
    • Source-synchronous seriel interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- USB HSIC PHY - High Speed Inter-Chip IP Core
  • USB 3.0 PHY IP, Silicon Proven in TSMC 7FF
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in TSMC 7FF
  • USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
    • Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    Block Diagram -- USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
  • USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    Block Diagram -- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in SMIC 14SF+
  • USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate
    • Supports 16-bit or 32-bit parallel interface
    • Data and clock recovery from serial stream
    Block Diagram -- USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in UMC 28HPC
  • USB 3.0 PHY IP, Silicon Proven in SMIC 14SF+
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in SMIC 14SF+
  • USB 3.0 PHY IP, Silicon Proven in UMC 40SP
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in UMC 40SP
  • USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in TSMC 28HPC+
×
Semiconductor IP