Multi-Protocol PHY IP
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Multi-Protocol PHY IP
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209
Multi-Protocol PHY IP
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MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2.
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MIPI D-PHY/LVDS Combo TX (Transmitter) for Automotive in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 1.1 for D-PHY
- Supports both high speed and low-power modes
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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10Gbps Multi-Protocol PHY IP (+PCIe 3.1)
- Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet
- LC tank PLL with a wide range of reference clock frequencies and SSC
- High-performance decision feedback equalization and adaptive CTLE
- Serial and parallel loop-back functions
- Available in X1 through X10 lane configurations
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10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
- Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
- Supports PCIe L1 sub-states
- Supports SRIS and internal SSC generation
- Supports internal and external clock sources with clock active detection
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MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
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SerialLite PHY with PCS
- Integrated PCS Layer
- Low power & area
- Test Silicon
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MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI® Specification for D-PHY Version 1.2
- Backward compatible with MIPI® Specification for D-PHY Version 1.1
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25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
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25G PHY, TSMC 7FF x4 North/South (vertical) poly orientation
- Supports 1.25 to 25.8 Gbps data-rate
- Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
