Standard cell IP for TSMC
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Standard cell IP
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118
Standard cell IP
for TSMC
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Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
- Nominal voltage of 0.75 V +/-10 %
- Low voltage of 0.45 V +/-10 %
- Track height: 7.5T
- Operating temperature: -40°C to 125°C
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PMK Library IPs at TSMC 28HPC+ Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
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PMK Library IPs at TSMC 22ULL Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
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PMK Library IPs at TSMC 12E Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
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LPKT Library IPs at TSMC 28HPC+ Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
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LPKT Library IPs at TSMC 22ULL Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
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HPKT Library IPs at TSMC 12FFC Process
- High performance optimization cells
- Skew cells to minimized critical path delay
- Small setup, fast CK-to-Q flip-flop cells
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ECO Library IPs at TSMC 28HPC+ Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
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ECO Library IPs at TSMC 22ULL Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
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ECO Library IPs at TSMC 12E Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)