Standard cell IP for TSMC
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Standard cell IP
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108
Standard cell IP
for TSMC
from 6 vendors
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CLICK - The universal solution of power gating for the whole SoC
- - Fully automated island kit generator
- - Automatic digital power switch controller TRC, single or distributed
- - Scripts for easier and faster implementation
- - Close or open ring implementation
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CLICK - The universal solution of power gating for the whole SoC
- - Fully automated island kit generator
- - Automatic digital power switch controller TRC, single or distributed
- - Scripts for easier and faster implementation
- - Close or open ring implementation
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Voltage Domain Interfacing Cells for use between power domains using core transistors.
- Easy Integration
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12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- No need for a voltage regulator
- Cells designed with 3.3 V thick-oxyde transistors to support a wide operating voltage range from 3.3 V +/-10% to 1.1 V +/-10%
- Custom characterization corners down to 1.1 V +/-10% can be provided
- Ideal for always on clock islets (RTC) and always on functional islets (voice recognition)
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9 track standard cell library at TSMC 55 nm
- Compromise for density and speed
- 9-Track high cells
- Only Metal 1 used for cell design
- Compatible with 1P3M SoC implementation
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7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
- Power consumption is divided by up to 5
- Standard cells optimized for low-power at the schematic level
- Battery life increases
- Decrease of heat and life stress of the circuit
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TSMC 0.13um 9track Standard Cell Library, 1.2v operating voltage
- TSMC 0.13um LOGIC SALICIDE FSG IMD (1P8M,1.2V/2.5V) (CL013G)
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
- Engineered for Synthesizability and Routability.
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TSMC N3P Source Sync 3DIO PHY
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including:
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TSMC N3P Source Sync 3DIO Library
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including: