Standard cell IP for TSMC

Compare 117 Standard cell IP for TSMC from 6 vendors (1 - 10)

PMK Library IPs at TSMC 28HPC+ Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
PMK Library IPs at TSMC 22ULL Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
PMK Library IPs at TSMC 12E Process
- Power-gating cells for domain shutdown
- Isolation cells to prevent unknown states that come from unpowered domains
- Data retention flip-flops
- Always-on cells powered by retention supply rail
- Level shifter cells for multiple voltage domain
LPKT Library IPs at TSMC 28HPC+ Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
LPKT Library IPs at TSMC 22ULL Process
- Multi-bit flip-flops to save power and area
- Fine grain cells provide a variety of drive strengths to improve design PPA (Power, Performance, Area)
HPKT Library IPs at TSMC 12FFC Process
- High performance optimization cells
- Skew cells to minimized critical path delay
- Small setup, fast CK-to-Q flip-flop cells
ECO Library IPs at TSMC 28HPC+ Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
ECO Library IPs at TSMC 22ULL Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
ECO Library IPs at TSMC 12E Process
- Ease-of-use, compatible to industrial EDA flow
- Combinational cells (Inverter, Buffer, NAND, NOR, AOI/OAI, XOR/XNR)
- Sequential cells (Scan Flip-flop, and Latch)
Synopsys Synthesizable 3DIO IP for Flexible Physical Implementation
- Optimized for heterogeneous integration in 3D stacking
- Enabling designers the flexibility and scalability to accelerate multi-die integration
- Optimal PPA architected to supporting 2.5D and 3D packages
- Versatile offering tuned for optimal use scenarios, including: