ZLIB compatible compression and decompession, with DMA and AXi interface

Overview

This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interfaces and compression/decompression engines.

ARCHITECTURE

Separate DMA engines for Scatter/Gather descriptors and data movement, alow non stop processing of data.

Key Features

100% ZLIB compatible
Fixed Huffman encoding
Subset of LZ77
Scatter/Gather DMA engine
Utilizes linked list of transfer descriptors
Compression and Decompression in one IP Core
Configurable Data Path to 32, 64 or 128 bit
Fully AXI-4 compatible
AXI-Light for register Interface
Separate clocks for engines and AXI interface

Benefits

High Performance
small footprint

Block Diagram

Applications

Deliverables

Verilog Source Code
Test Bench
Documentation
Tech Support

Technical Specifications

Foundry, Node

any

Maturity

Silicon Proven

Availability

now

Request Info

Related IPs

AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
HASH Core, providing MD5, SHA1 and SHA256. Includes DMA and AXI Interface
UART with FIFOs and Synchronous CPU Interface
UART with FIFOs, IrDA and Synchronous CPU Interface
AES Crypto and SHA-2 Hash Core with DMA
1G to 50G Single-Port MACsec Engine with xMII interface and TSN support