XSPI Master IIP

Overview

XSPI Master interface provides full support for the two-wire XSPI Master synchronous serial interface, compatible with XSPI specification. Through its XSPI Master compatibility, it provides a simple interface to a wide range of low-cost devices. XSPI Master IIP is proven in FPGA environment.The host interface of the XSPI Master can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

XSPI Master IIP is supported natively in Verilog and VHDL

Key Features

Compliant with XSPI protocol of JEDEC standard version 1.0 specification
Support single master and multiple slaves per interface port
Support source synchronous clocking
Support Deep power down enter and exit commands
Support Eight IO ports in standard. Possible to increase IO port based on system performance requirements
Optional support for Data strobe for write masking
Support 1-bit wide SDR transfer
Support profile 1.0 Commands to manage a non-volatile memory device
Support profile 2.0 Commands to support read or write data for any time of slave devices
Speed grades with data transfer rates up to

400MT/s (200 MHz Clock)
333MT/s (167 MHz Clock)
266MT/s (133 MHz Clock)
200MT/s (100 MHz Clock)

To support protocol modes:

1S – WR –WR
4D – 4D – 4D
8D – 8D – 8D

Transaction phases – Command, Address, Latency, Data
Transfer bit width options in each phase W = 1 or 8
Data rate options in each phases S for SDR or D for DDR
Has inbuilt Host controller Interface (DMA Engine)
Supports legacy SPI Devices on same device
Fully synthesizable.
Static synchronous design.
Positive edge clocking and no internal tri-states.
Scan test ready.
Simple interface allows easy connection to Microprocessor/Microcontroller devices.

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The XSPI Master interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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