SBWP Master IIP

Overview

SBWP Master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Safe-by-Wire Plus Specification. Through its SBWP compatibility, it provides a simple interface to a wide range of low-cost devices. SBWP Master IIP is proven in FPGA environment. The host interface of the SBWP Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SBWP Master IIP is supported natively in Verilog and VHDL

Key Features

Compliant with version 2.0 Safe-by-Wire Plus Specifications
Full SBWP Master functionality
Supports occupant restraints bus for deployable devices and for sensors
- Deployment bus for squibs and optionally for static occupancy sensors
- sensor bus for smart or simple impact sensors, dynamic occupancy sensors and optionally for static occupancy sensors
- combined sensor / deployment bus
Supports Bi-directional two-wire bus with integrated power distribution
- Master-Slave operation
- Babbling-idiot protection for deploy messages from master
- Provides optional interrupt possibilities for smart impact sensors
- Optional multi-master operation
Supports variable bus speed with self-clocking slaves
- 20 kbps, 40 kbps, 80 kbps or 160 kbps +/- 13%
- Data throughput example: at 160 kbps, (=160 kHz):
* Transfer time of a deploy message controlling up to 12 deployable devices < 200 μs
* Transfer time for retrieving 8-bit data from 3 impact sensors < 250 μs
- Supports, but does not require, speed change for high-speed deployment messages, initiated by the master
- Supports, but does not require, speed change for high-speed sensor polling messages, initiated by sensors ("interrupt" from sensor)
Supports flexible bus topologies: bus, tree, ring, mixed
Allows design of daisy chain systems, parallel systems and mixed systems
- Bus length of parallel systems up to 40 m
- Bus length of daisy-chain systems up to 25 m
Supports real-time recovery from single-point bus shorts to any voltage within specified range
Supports communication error detection by transmitter (data read-back) and by receiver (CRC)
Supports multi-level protection against inadvertent deployment
- Detection of bit errors by master and by slave
- Special bus level reserved for deploy messages ("analog safing")
- Deployment only possible after charging of the energy reserve capacitor (ERC) in the deployable device
- Deployment only possible when deploy-enable message has been sent before
- Supports the use of two deploy switches, which can be controlled and diagnosed independently over the bus
Allows the use of small hold-up capacitors in the slaves
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to Microprocessor/Microcontroller devices

Benefits

Single Site license option is provided to companies designing in a single site.
Multi Sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The SBWP Master interface is available in Source and netlist products.
The Source product is delivered in verilog. If needed, VHDL and SystemC can also be provided
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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