XPS Serial Peripheral Interface
Overview
The XPS Serial Peripheral Interface (SPI) connects to the PLB (Processor Local Bus) and provides a serial interface to SPI devices such as SPI EEPROMs. The SPI protocol, as described in the Motorola M68HC11 data sheet, provides a simple method for a master and a selected slave to exchange data.
Key Features
- Connects as a 32-bit slave on PLB V4.6 buses of 32,
- Supports four signal interface (MOSI, MISO, SCK and SS)
- Supports slave select (SS) bit for each slave on the SPI bus
- Supports full-duplex operation
- Supports master and slave SPI modes
- Supports programable clock phase and polarity
- Optional transmit and receive FIFOs
- Optional transmit and receive FIFOs scanning of a peripheral
- Supports back-to-back transactions
- Supports automatic or manual slave select modes
- Supports local loopback capability for testing
Technical Specifications
Related IPs
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
- Express Serial Peripheral Interface IP Core
- Serial Peripheral Interface - Master/Slave
- Serial Peripheral Interface
- Serial Peripheral Interconnect Master & Slave Interface Controller