VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple DUP I/O
Overview
VeriSilicon GSMC 0.18μm 1.8V/3.3V Multiple DUP I/O Cell (01E) Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18μm Logic 1P6M Salicide 1.8/3.3V process. This library supports inline DUP I/O pads. With configurable output driving strength and selective output slew rate control, this library can work with different IO supply operating voltages from 1.8v to 3.3v.
Key Features
- Process: Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P6M Salicide 1.8/3.3V process
- Supply voltage:
- ------1.62V~3.6V for I/O supply
- ------1.8V for core power supply
- Configurable output driving capability, min/max driver current is 2mA/16mA at 3.3v power supply
- Supports configurable pull-up and pull-down resistor
- Supports Schmitt-trigger input and CMOS input
- Selective output slew rate control
- Provides bi-directional, input only, output only and bi-directional buffer with pull-up only pads
- Suitable for four, five or six metal layers of physical design
- Easy interface with VeriSilicon GSMC 0.18um process standard I/O libraries
- Supports 60μm pitch inline DUP pad layout, cell height is 110um
Deliverables
- Databook in electronic form
- Verilog models and Synopsys synthesis models
- Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist
Technical Specifications
Foundry, Node
GSMC, 0.18um
Maturity
Available on request