Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfaces
Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics. PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation. Avery compliance test suites offer effective core-through-chip-level tests, including those used in compliance workshops as well as extended tests developed by Avery to cover the specifica tion features.
Specifications
|
Protocol Family |
Standard Organization |
Sub Protocol |
Models |
|---|---|---|---|
|
UCIe |
Universal Chiplet Interconnect Express (UCIe) |
UCIe 1.0 |
