USB IP

Key Features

  • Verilog Implementation on RTL Level
  • Supports both Full Speed (12Mbps) and Low Speed (1.5Mbps).
  • The Core will perform all USB enumeration in hardware
  • All interface are architecture as FIFO based model.
  • CRC generation and checking
  • Physical Layer Interface
  • Avalon Interface Compliant

Deliverables

  • USB1.1 Evaluation Package
    • Encrypted Code
    • Windows 2k /Xp Driver and Software (Executable)
    • SLS Port Interface Application (Executable)
    • Nios USB Application.
    • Snap On Board
    • Driver API
    • Three Months Open Cores Plus License (renewable for free)Open Cores Plus means that a JTAG cable must be connected to the target system in order for the FPGA system to work.
  • USB1.1 Full Package :
    • Encrypted Code
    • Windows 2k /Xp Driver and Software (Executable)
    • SLS Port Interface Application (Executable)
    • Nios USB Application.
    • Snap On Board
    • Driver API
    • Unlimited Open Cores License for single site(location) for 1 Year including e-mail support for integration issues.Open Cores means that the JTAG cable is no longer required and the system may operate standalone.

Technical Specifications

Availability
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Semiconductor IP