Ultra-Compact Data Encryption Standard (DES/3DES) Core

Overview

The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard. It processes 64-bit blocks, with one, two, or three 56-bit keys.

Basic core is very small (3,000 ASIC gates). Enhanced versions are available that support
various cipher modes (ECB, CBC, OFB, CFB,
CTR).

The design is fully synchronous and available in both source and netlist form. Test bench
includes the NIST DES test vectors.

DES Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

Key Features

Encrypts and decrypts using the DES / TDEA / Triple DES / 3DES Block Cipher Algorithm
High throughput: up to 3 Gbps at 750 MHz in 90 nm LV technology
Small size: from 3K ASIC gates for a triple DES core
Satisfies FIPS 46-3 from the US National Institute of Standards and Technology (NIST)
Processes 64-bit data blocks
Employs one to three keys of 56 bits each
Completely self-contained: does not require external memory
Available as fully functional and synthesizable Verilog, or as a netlist for popular programmable devices and ASIC libraries
Deliverables include test benches

Block Diagram

Deliverables

HDL Source Licenses

Synthesizable Verilog RTL source code
Testbench (self-checking)
Test vectors
Expected results
User Documentation

Netlist Licenses

Post-synthesis EDIF
Testbench (self-checking)
Test vectors
Expected results

Technical Specifications

Availability

Now

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