TSMC CLN65GP 65nm Ultra PLL - 15MHz-3000MHz
Overview
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, features and ease of use. It is highly programmable so one PLL can be used for all applications on a SoC. It has ultra-low jitter performance (<500fs) for the most demanding SerDes and ADC reference clocks. It has ultra wide frequency range with multiplication factors over 250,000 to support reference clocks from 32KHz to 1GHz. It has precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution. It can generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements. It draws low power in a compact size.
Key Features
- New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
- Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
- Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
- Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.
- Optional spread spectrum support with programmable rate and depth to meet tight FCC requirements.
- Low power and compact size.
- Highly programmable so one PLL can be used for all applications on a SoC.
Deliverables
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
- User Guidelines including:
- integration guidelines,
- layout guidelines,
- testability guidelines,
- packaging guidelines,
- board-level guidelines
Technical Specifications
Foundry, Node
TSMC CLN65GP
TSMC
Pre-Silicon:
65nm
GP