IGADACV02A is a general-purpose 3-channel digital-to-analog converter with 12-bit resolution. The data output rate is up to 500 MHz. The input digital code is unsigned binary.
IGADACV02A contains 3 current steering DAC circuits and relative digital decoders. The analog output currents of DAC per channel are maximum differential +/-4 mA. Power-down mode is available to disable the DAC and lower down the power consumption. IGADACV02A is designed for TSMC CLN12FFC 0.8 V/1.8 V. The supply voltage 0.8 V is used for digital circuits, and 1.8 V/0.9 V is used for analog circuits.
The power-down and stand-by modes are available to disable the DAC or lower down the power consumption.
TSMC CLN12FFC 12-bit 500MHz Current Steering DAC
Overview
Key Features
- TSMC 12 nm 0.8 V / 1.8 V CMOS LOGIC FinFET Compact Process
- Metal scheme: 1P9M (2Xa1Xd_h_3Xe_vhv_2Z)
- Operating junction temperature: -40 °C ~ 125 °C
- 1.8 V / 0.9 V analog supply operation and 0.8 V digital supply operation
- Maximum sampling rate: 500 MHz with 12 bit resolution
- Maximum current output per channel Idpp = +/-4 mA (differential)
- Maximum output signal swing: Vdpp= 1 V (+/-0.5 V, single-end)
- SINAD > 66 dB Fin=40 MHz, -1 dBFS input
- SFDR > 70 dBc Fin=40 MHz, -1 dBFS input
- THD<-66 dBc Fin=40 MHz, -1 dBFS input
- Gain mismatch: 0.2 dB
- Phase mismatch: +/-0.2 degree
- Support power-down mode, and standby mode
- Special layer and device: I/O device, core device(svt and ulvt), HR-resistor
- IP GDS size: 770 um (width) x 660 um (height)
Technical Specifications
Foundry, Node
TSMC 12nm CLN12FFC
Maturity
Pre-silicon
TSMC
Pre-Silicon:
12nm
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