Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
Overview
UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library.
Technical Specifications
Short description
Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 55nm LP
UMC
Pre-Silicon:
55nm
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