Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process
Overview
UMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library.
Technical Specifications
Short description
Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP
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