SATA 2 HOST ON CYCLONE 5 GX
Overview
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The LDS SATA 2 HOST_C5GX IP is compliant with Serial ATA II specification and signaling rate is 3Gbps and scalable 1.5Gbs. The LDS SATA 2 HOST C5GX IP is fully synchronous with system frequency (Clock_sys) at 75MHz in case of 3Gbps speed and 37.5MHz in case of 1.5Gbs speed configuration. The VHDL source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
Key Features
- Rate Match FIFO
- Manage SATA reference frequency difference between the FPGA and the Disk
- Physical Layer features
- Detect OOB and COMWAKE
- Detect the K28.5 comma character and provide a 32 bit parallel output
- Power management mode handled by state machine (shared between Phy and Link layer)
- Provides error indication to upper layers
- 8b/10b encoding and decoding
- Fixed Speed 3Gbs or 1.5Gbs
- Link Layer features
- Scrambling of TX data and descrambling of RX data
- CRC 32 calculation and check
- Report transmission status and error to Transport Layer
- Enable BIST Retimed loopback and pattern generation modes
- Auto inserted hold primitive to avoid FIFO overflow and underflow
- Partial and slumber power management modes
- The interface between the link layer and the transport layer is 32-bit wide
- Transport Layer features
- 48-bits sector address
- Programmed IO (PIO) and DMA modes
- Support BIST FIS transmission and reception
- Automatic error FIS retry capability
- Implement Shadow Registers and SATA SuperSet registers
- Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
- DMA interface can be connected easily to memory space or FIFOs
- 128-Word Ingress and Egress FIFO between Transport and Link Layer
- NCQ Support
Block Diagram
Technical Specifications
Maturity
Good
Availability
Now