IP Catalog > Peripheral IP > SPI IP > POS-PHY Level 4

POS-PHY Level 4

Overview

The packet over SONET/SDH PHY (POS-PHY) Level 4 interface, first developed by the SATURN Development Group, was later adopted by the Optical Internetworking Forum (OIF) as the System Packet Interface Level 4-Phase 2 (SPI-4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.

The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed cell and packet transfers between PHY and link-layer devices. The SPI-4.2 interface supports a data width of 16 bits (LVDS solution), and can be a PHY-link, link-link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including ATM and POS (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel gigabit and fast Ethernet.

Key Features

  • Configurable datapath width (32 bits, 64 bits, 128 bits)
  • Supports up to 256 ports
  • POS-PHY Level 4 MegaCore® function throughput rate:
    • From 840 Mbps to 1,250 Mbps per LVDS lane for Stratix® series FPGAs and HardCopy® series ASICs
    • Up to 840 Mbps per LVDS lane for Arria® GX series FPGAs
    • From 250 Mbps per LVDS lane (32-bit system datapath) to 622 Mbps (64-bit system datapath) for Cyclone® series FPGAs
  • Fixed start of packet (SOP) alignment to the most significant byte lane eases subsequent packet processing
  • FIFO buffer status management and indications
  • Run-time programmable calendar length, burst size, and threshold levels
  • Asymmetric ports and hitless bandwidth re-provisioning
  • Error detection and handling
  • Easy-to-use intellectual property (IP) toolbench interface and functional simulation models in Verilog and VHDL

Benefits

  • SOPC Builder Ready: No
  • Qsys Compliant: No

Technical Specifications

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