IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI PHY IP > MIPI C-PHY/D-PHY Combo IP > MIPI RX CPHY_v1.2 / DPHY_v1.2, 3-TRIO/1C4D, TSMC 16FFC, E/W orientation

MIPI RX CPHY_v1.2 / DPHY_v1.2, 3-TRIO/1C4D, TSMC 16FFC, E/W orientation

Overview

MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve throughput over bandwidth limited channel, the C-PHY is developed and is delivering 2.28 bits per symbol over three-wire trio. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides a silicon-proven, low-power and low cost C-PHY/D-PHY combo IP on various process nodes. Users can configure the PHY into D-PHY mode or C-PHY mode to support different applications using the same PHY. It is compliant to the PPI interface which allows seamless integration with upside controllers for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols.

Key Features

  • Compliant with MIPI D-PHY v1.2 and C-PHY v1.2 specs
  • Support both MIPI DSI and CSI-2 protocols
  • Support HS data rate from 80Mbps (0.8Gsps) up to 2.5Gbps (3.5Gsps) per lane (per trio)
  • Support LS data rate of 10Mbps and Ultra-low power mode
  • Support D-PHY mode with 1 clock lane & up to 4 data lanes
  • Support C-PHY mode up to 3 trios for TX and 4 trios for RX
  • Support TX-EQ function to compensate loss of a long channel
  • Support additional D-PHY RX mode with 2 sets of (1 clock lane and up to 2 data lanes)
  • Support additional C-PHY RX mode with 2 sets of 2 trios
  • Provide D-PHY clock and data lane swap function
  • Provide C-PHY trios swap function
  • Provide a stand-alone at-speed multi-lanes (trios) parallel BIST module for mass production tests

Block Diagram

MIPI RX CPHY_v1.2 / DPHY_v1.2, 3-TRIO/1C4D, TSMC 16FFC, E/W orientation Block Diagram

Technical Specifications

Foundry, Node
TSMC 16FFC
TSMC
Pre-Silicon: 16nm
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