MIPI D-PHY Universal IP in UMC 40LP

Overview

The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low powerfunctions are mostly used for control.

Key Features

Consists of 1 Clock lane and up to 4 Data lanes
Supports the MIPI Standard 1.1 for D-PHY
Supports both high speed and low-power modes
80 Mbps to 1.5Gbps data rate in high speed mode
10 Mbps data rate in low-power mode
High Speed Serializers and Deserializers included
Low power dissipation
Loopback testability support
Optional resistance termination calibrator

Benefits

Supports both MIPI CSI-2 and MIPI DSI, as a transmitter and receiver
Silicon proven in UMC 40LP

Block Diagram

Video

Mixel Customer Demo - Lattice Crosslink FPGA Video Bridge

We demonstrate our customer demo, the Lattice Crosslink FPGA Video Bridge, featuring Mixel's MIPI D-PHY Universal IP.

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

UMC, 40LP

Maturity

Silicon Proven

Availability

Now

UMC

In Production: 40nm LP
Silicon Proven: 40nm LP

Request Info