MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane

Overview

The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 specifications, with up to 8 data lanes, at up to 2.5GBPS per lane. Total available bit rate is 20Gbps, supporting, for example, 7680x4320 (8K) images at 60fps

Key Features

One clock lane, and from 1 to 8 data lanes
Simple interface – legacy parallel-video input, augmented by an Early-HD signal
Input interface – parallel 1, 2 or 4 pixels per clock
Can support any or all CSI2 2.0 pixel formats
Uses simple off-FPGA analog front-end – passive or active.
DPCM compression scheme according to CSI2 specification Annex A
Calibration Packet generation.
Easy-to-use Excel programming guide provided with the IP
Comprehensive customer support, until IP integration is successfully completed

Benefits

Up to 20GBps using DPHY 1.2
Simple user interface
interface to passive component or active off-FPGA analog front end
Supports pixel compression
Highly customized - can support any or all CSI2 video formats
1,2 or 4 pixels per clock - allowing to trade lower internal clock rate for FPGA resources

Deliverables

Verilog RTL
SDF
Documentation
Programmer Guide (Excel)

Technical Specifications

Maturity

New Product

Availability

Now

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