LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
Overview
LVDS RX, UMC 40nm LP/RVT Low-K Logic process.
Technical Specifications
Short description
LVDS Receiver IP, Clock: 16 MHz - 120 MHz, 6:42 data lane expansion for throughput up to 5040 Mbps, UMC 40nm LP process
Vendor
Vendor Name
Foundry, Node
UMC 40nm LP
UMC
Pre-Silicon:
40nm
LP