LogiCore AXI to AHB-Lite Bridge IP

Overview

Included at no additional charge with Vivado Design and System edition of software. Also available as part of IDS Embedded Edition (EDK)

The Xilinx LogiCORE™ IP AXI to AHBLite Bridge controller is a bridge IP that translates AXI-4 transaction to AHB Lite transactions. It functions as slave on AXI-4 interface and master on AHB-Lite interface. This bridge IP is required to connect any AHB-Lite slave in AXI-4 based system.

Key Features

  • Connects as a 32/64-bit slave on 32/64-bit AXI4
  • Supports
    • 1:1 (AXI:AHB) synchronous clock ratio
    • Incrementing burst transfers (length 1 to 256)
    • Wrapping burst transfers (length 2, 4, 8, and 16)
    • Fixed burst transfers (of length 1 to 16)
    • Narrow transfers
    • Address/data phase timeout
  • AHB-Lite Master Interface:
    • Connects as a 32/64-bit master on 32/64-bit AHB-Lite interface
  • Supports:
    • Single burst transfers
    • Wrapping burst transfers (length 4, 8, and 16)
    • Incrementing burst transfers (length 4, 8, 16) , and undefined burst length
    • Limited protection control
    • Narrow transfers

Technical Specifications

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Semiconductor IP