JPEG Extended Encoder

Overview

This IP core has been developed to be a complete standards compliant JPEG Extended Encoder.

Extended and Baseline DCT compression according to JPEG ITU-T T.81 | ISO/IEC 10918-1 standard.
JFIF 1.02 standard file header.
HDR: from 8 to 36 bpp (bits per pixel) pixel data width, runtime selectable, RGB and YCbCr.
On-the-fly selectable quality level/compression ratio from 1 to 100 to achieve any bitrate.
Drag'n'drop IP block for Xilinx Vivado Block Design and Intel Quartus Qsys.
Constant throughput: 1 pixel per cycle grayscale, or 2 compressed pixels every 3 clock cycles color
Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
Optional SW control of the IP core configuration registers (sample source code provided)
Selectable JPG chroma subsampling (4:4:4, 4:2:2, 4:2:0), independent of input subsampling.
Unlimited image resolution (up to 64K x 64K as per JPEG spec.).
Unlimited Restart markers support.