Inverter based delay chain, 10ns
Overview
Inverter based delay chain, 10ns
Technical Specifications
Foundry, Node
TSMC 180nm
Maturity
Silicon Verified
TSMC
Pre-Silicon:
180nm
,
180nm
E
,
180nm
ELL
,
180nm
FG
,
180nm
G
,
180nm
LP
,
180nm
LV
,
180nm
ULL
Related IPs
- Inverter based delay chain, 5ns
- Rising edge delay cell for control circuits, 10ns - TSMC 180nm
- 10ns rising edge delay circuit, RC-based, trimmable
- Clock generator, 180MHz~300MHz based PLL
- Clock generator, 300MHz~500MHz based PLL
- Clock generator, 300MHz~500MHz based PLL, with lock detection and free running