The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolution and Dual Link transmission between Host and Flat Panel Display with up to UXGA resolution.
The IP converts 70-bit of CMOS/TTL data into LVDS data stream. The transmitter can be programmed for rising edge or falling edge clocks via a dedicated pin.
IBM 65nm LVDS Transmitter
Overview
Key Features
- Supports 20MHz ~ 92MHz clock
- 35:5 data channel compression ratio at up to 650Mbps per channel data rate
- Supports single pixel and dual pixel interfaces
- Converts 70 bits data to 10-pair LVDS data stream
- No special start-up sequence required between clock/data and PD pins
- Supports Spread Spectrum Clocking up to 100kHz frequency modulation & deviations
- of ±2.5% center spread or -5% down spread
- No external component required for PLL
- Clock edge selectable
- Compatible with the TIA/EIA-644-A LVDS standard
- Power down mode
- Full industrial operating temperature range: -40 ~ +125℃
- IBM CMOS 10SF Process (1.0V/2.5V)
Technical Specifications
Foundry, Node
IBM 65nm
Maturity
Silicon Proven
Related IPs
- LVDS Transmitter 1250Mb/s, 800Mhz clock with RSDS support
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane
- IBM 65nm LPE 3.3V
- IBM 65nm 12-Bit 8-Input 1M/200k SAR ADC
- IBM 10SF 65nm 2.5v PLL
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression