I3C Prototyping Kit (HDK) Total IP in a Box
Overview
The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box. The HDK contains I3C Master and Slave FPGA Boards programmed with Arasan’s I3C Master & Slave IP respectively, I3C software stacks and reference schematics. The HDK will also be compatible with open source I3C drivers. Arasan’s I3C IP Cores are fully configurable across multiple parameters through simple scripts making it suitable for a variety of Sensor applications. Arasan’s I3C IP has been validated at the RTL with multiple I3C VIP vendors and the System Level at MIPI Interoperability Sessions with participation from the major companies actively implementing the I3C specifications. This ensures Arasan’s I3C IP is interoperable with multiple vendor solutions and is compliant to the specifications.
Key Features
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
- Open-Drain and Push-pull type transactions (as required)
- Supports legacy I2C devices.
- Dynamic Addressing while supporting Static Addressing for Legacy I2C devices
- Legacy I2C Messaging
- I2C-like Single Data Rate Messaging (SDR)
- Optional High Data Rate Messaging Modes (HDR)
- Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present).
- Reception of In-band Interrupt Support from the I3C Slave devices
- Reception of Hot-Join from newly added I3C Slave devices.
- Synchronous Timing Support and Asynchronous Time Stamping.
- APB/AHB Target Interface for Configuring/Controlling the IP with Interrupt output.
- Small 16-byte (Configurable) FIFO for transferring data between Master and the Slave devices.
- Independent Clocks for AHB and the I3C Interface.
Block Diagram
Deliverables
- Arasan I3C Master and Slave IP programmed in Xilinx FPGA
- Arasan I3C Master and Slave IP PCB Development Boards with connector cables
- I3C Linux Software Stack and firmware
- Reference PC
Technical Specifications
Maturity
Silicon proven
Availability
NOW
Related IPs
- UFS Host 3.0 Prototyping Kit (HDK )Total IP in a Box
- UFS Host 2.1 Prototyping Kit (HDK )Total IP in a Box
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- 2D (vector graphics) & 3D GPU IP A GPU IP combining 3D and 2D rendering features with high performance, low power consumption, and minimum CPU load
- DDR3/ DDR3L Combo PHY IP - 1600Mbps (Silicon Proven in UMC 40LP)
- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)