The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking customers to add features like quality of service (QoS), port trunking, mirroring across devices, and link aggregation at higher layers of the OSI network model. The HiGig™ MAC ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig™ Protocol definitions are met while transmitting a frame of data over Ethernet. On the receive side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface.
The HiGig™ / Ethernet MAC IP core is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased. The HiGig™ MAC IP core from Lattice supports the LatticeECP3 and LatticeSC/M FPGA families.
HiGig™, HiGig2™ are trademarks of Broadcom Corporation.
HiGig Ethernet MAC
Overview
Key Features
- Compliant to the Broadcom HiGig and HiGig2 Protocol Definitions
- 64-bit wide internal data path operating at a maximum frequency of 187.5 MHz (LatticeECP3 maximum 156 MHz)
- XGMII interface to the PHY layer (using IODDR external to the core)
- XAUI interface to the PHY layer (using PCS/SERDES external to the core)
- Simple FIFO interface with user’s application
- Optional multicast address filtering
- Transmit and receive statistics vector
- Optional statistics counters of length from 16 to 40 (external to the core)
- Variable-sized packet transmission with fixed sized messaging capability (HiGig2 Only)
- Programmable Inter Frame Gap
- Supports:
- Full duplex operation
- Flow control using PAUSE frames (for HiGig) and messaging (for HiGig2)
- Automatic padding of short frames
- Optional FCS generation during transmission
- Optional FCS stripping during reception
- Jumbo frames up to 16k
- Inter frame Stretch Mode during transmission
- Deficit Idle Coun
Block Diagram
