High Performance / Low Power Microcontroller Core

Key Features

• 8-Bit Synthesizeable Microcontroller Core
• Opcode Equivalent to Industry Standard 8051
• Fully Static, Microcode Free Design
• Pipelined Design - the execution unit runs independent from the instruction fetch unit
• independent programmable Wait State Generators for ROM access and RAM access
• Up to 64K Bytes Program Memory Address Space
• Up to 64K Bytes Data Memory Address Space
• Up to 256 Bytes Internal Data Memory
• Up to 128 Special Function Registers (SFR)
• Idle, Power Down Mode
• Up to 15 Interrupt Sources in four Priority Levels
• Two Data Pointer
• 1.7 cycles per Instruction
• 300MHz max clock freq. with 0.25µm
• ~4500 gate equivalents
• ~0.11mm² core size with 0.25µm
• 0.05mW / MHz

Deliverables

• Technology Independent Implementation (Verilog Source Code)
• Verilog Simulation Models
• Verilog 8051 Compliance Test Suite
• Synthesis and Testsynthesis Scripts
• Design Support, Netlist Synthesis Service and Consulting available

Technical Specifications