HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol.
The hardware components are fully synchronous and available as Verilog source. The software components are available in C language.
HDCP 2.0 Encryption Suite
Overview
Key Features
- Support for HDCP 2.0
- Support for all HDCP configurations:
- HDCP Transmitter (-TX)
- HDCP Receiver (-RX)
- HDCP Repeater (-RPT)
- Implementation of the HDCP Authentication protocol:
- Authentication and Key Exchange (AKE)
- With Key Derivation
- Locality Check
- Session Key Exchange (SKE)
- Authentication with Repeaters
- Authentication and Key Exchange (AKE)
- Data encryption:
- Utilizes HDCP Cipher (AES-128-CTR)
- Includes the Link Synchronization
- Transmitter and Receiver utilize the counter information in the PES Private Data
- FIFO-like flow-through interface with flexible bit width; simple integration into the datapath.
- Microprocessor-friendly interface for programmable I/O is optional
- Components
- HDCP software written in C (CPU subsystem is not included)
- Hardware accelerators
- AES1-CTR-HDCP: AES encryption/decryption capable of handling the PES streams
- RSA2: An RSA hardware accelerator (optional, high-end CPUs can use the software implementation)
- TRNG1: A true random number generator (optional, if entropy bits are available in the design, a software implementation can be used)
- SHA2-256: A Sha-256 hash accelerator (optional, most CPUs can use the software implementation)
Block Diagram
Applications
- Digital rights management (DRM)
- HDCP 2.0 implementations for generic wired and wireless interfaces