High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.
Floating-point Square-root
Overview
Key Features
- 32-bit floating-point arithmetic
- IEEE 754 compliant
- High-speed fully pipelined architecture
- FPGA clock rates of 300 MHz+
- Trade off latency vs. speed
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All
Availability
Immediate