DDR5 DIMM Memory Model

Overview

Key Features

• Supports DDR5 DIMM memory devices from all leading vendors.
• Supports 100% of DDR5 DIMM protocol standard.
• Supports DDR5 RDIMM and LRDIMM types.
• Supports all the DDR5 DRAM features.
• Supports up to 64GB device density.
• Supports the following devices.
  • X4
  • X8
  • X16
• Supports all speed grades as per specification.
• Supports CA, CS and Read Preamble training modes.
• Supports MIR, CAI and 2N mode operations.
• Supports Read training pattern.
• Supports Write leveling training mode.
• Supports Programmable Write latency and Read latency.
• Supports Programmable Preamble, Postamble and Interamble.
• Supports Programmable burst lengths: 8, 16 and 32.
• Supports Sequential burst type and Burst order.
• Supports all mode register programming.
• Supports Write data mask and Write Pattern command.
• Supports CRC for Write, Read and MRR operations.
• Supports Self Refresh and Power down operation.
• Supports Self Refresh Entry with frequency change (SREF)
• Supports Refresh modes and Global refresh counter.
• Supports Refresh management all command.
• Supports Refresh management same bank command.
• Supports Maximum power saving mode.
• Supports Post Package Repair (PPR).
• Supports Target row refresh and Loop back concepts.
• Supports per DRAM Addressability and DLL features.
• Supports Precharge command modes.
• Supports Multipurpose Command (MPC).
• Supports VrefCA and VrefCS commands.
• Supports VrefCA, VrefCS and VrefDQ training.
• Supports ZQ calibration and Connectivity Test (CT) mode.
• Supports input clock stop and frequency change.
• Supports On-Die Termination (ODT)
• Checks for following
  • Check-points include power up, initialization and power off rules
  • State based rules, Active Command rules
  • Read/Write Command rules etc.,
  • All timing violations
• Supports all timing delay ranges in one model: min, typical and max.
• Protocol checker fully compliant with DDR5 DIMM Specification.
• Constantly monitors DDR5 DIMM behavior during simulation.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

Benefits

• Faster testbench development and more complete verification of DDR5 DIMM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

Block Diagram

Deliverables

• Complete regression suite containing all the DDR5 DIMM testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.

Technical Specifications