CXL Host Device Dual mode controllers

Overview

Key Features

• Compliant to CXL spec V1.1.
• Compliant to PCIE spec 5.0.
• Compliant to AXI 5.0.
• Configurable AXI master(512bit), AXI slave(512bit). PIPE/FLEX bus 64b/32b.
• Configurable to work as standalone PCIE DM/CXL DM. Configurable to work as standalone PCIE DM/CXL DM. Configured as PCIE RP/PCIE EP/CXL RP/CXL EP. Native PCIE support.
• CXL mode / PCIE mode.
• Static config of PCIE vs CXL.
• Rate 8/16/32 GT/s in CXL mode and 2.5/5/8/32 in PCIE mode. Configurable X16, X8, X4, X2, X1.
• Single protocol selector.
• Configurable multiprotocol of CXL.io/CXL.cache/CXL.mem. Type 1/2/3 CXL devices supported.
• Host Bias / Device Bias supported.
• PCIE Power management using VDM.
• Configurable credits with granularity of 128 bits. Configurable VCs.
• ATS support for type1, type2 devices.
• AER support.
• Data poisoning.
• Memory request to limited region through IO.
• Deferrable writes support.
• Viral info support.
• Alternate protocol negotiation.
• Round robin / Weighted arbitration support in DL TX.

Benefits

• Easy to integrate
• Efficient architecture
• Good timing met in ASIC and FPGA

Deliverables

• Digital IP code in verilog
• UVM VIP
• Hardware validation platform FPGA

Technical Specifications