Controller Area Networks, CAN 2.0B Bus Controller IP Core
Overview
CAN is part of HCL’s IP offerings and supports Version 2.0, PART B specification released by Bosch. This IP supports standard FIFO interface at application side and standard interface that would get connected to CAN Transceiver. It offers a simple register interface for communication with host. This register interface can be customized quickly if needed, for other leading industry standard bus interface to host such as Avalon, AXI4 – Lite, AHB, and APB. This IP is efficient and functionally verified and well tested design for the CAN (Version 2.0, PART B) and can be immediately used in SoC designs in need of the CAN Interface.
Key Features
- Compliant to CAN 2.0B protocol
- Support of up to 8 High Priority and up to 16 Low Priority messages on the CAN Transmit side
- Supports up to 32 Identifier registers which along with corresponding Mask registers can be used to filter variety of messages on the CAN Receiver side
- Supports Extended as well as Standard Identifiers
- Supports programmable baud rate using prescalar configuration register with 1Mbps as maximum data rate supported
- Provides programmable registers for CAN Timing
- Includes different statistic counters providing information for diagnostic purposes
- Supports interrupt generation
- Supports listening mode
Benefits
- This IP is efficient and functionally verified and well tested design for the CAN (Version 2.0, PART B) and can be immediately used in SoC designs in need of the CAN Interface.
Block Diagram
Applications
- Automotive
Deliverables
- User Manual
- Source Code – SystemVerilog HDL
- Reference Verification Environment (UVM Based)
- Synthesis Scripts
- Timing Constraints
Technical Specifications
Foundry, Node
40nm
Availability
Now