Compact 32-bit MCU core for deeply embedded applications and accelerator control

Overview

Key Features

• 32bit microcontroller core with RISC-V ISA
• RV32I|E[MC]
• Harvard architecture, separate Instruction and Data memories
• 32 or 16 32bit integer registers
• RV32I or E basic instruction set, optional M and C extensions
• 47 Integer (32bit encoding) instructions
• 47 E instructions (subset of I, restricted to 16 registers)
• 27 Compact (16 bit encoding) instructions
• 8 Optional Multiply/Divide instructions
• 15 kGates in basic fully functional configuration (ICE)
• Includes IRQ controller and debug
• 32bit AHB-compliant external interface
• 2 to 4 stages pipeline
• Machine-mode only
• Embedded 64bit RTC timer
• Tightly Coupled Memory (TCM) support
• 4..64KB
• Optional configurable Integrated Programmable Interrupt Controller (IPIC)
• Low interrupt latency
• 8..32 IRQs
• Optional area-optimized MUL/DIV unit
• Optional integrated Debug Controller
• with JTAG-compliant interface

Block Diagram

Deliverables

• Verification suite
• Testbench, tests, tracelog
• Documentation
• Basic simulation and synthesisenv
• Reference design
• Open FPGA-based SDKs

Technical Specifications