The Chip-to-Chip IO Buffer is a general purpose IO for medium-speed per lane transactions in ultra- short reach environments, using single-ended switching for efficient high-density utilization of available inter- chip routing tracks. It features core-voltage-level signal switching for low power and high voltage margin, and an unterminated receiver allowing for maximum signal swing at lowest power in ultra-short reach environments.
The output is tristateable allowing for bi-directional signal flow.
The output driver is implemented in Analog Bits’ proprietary architecture that uses core devices only.
Chip-to-Chip IO Buffer Characteristics Description Symbol Min Typ Max Units I/O Bit Rate FCLK 0 1000 Mb/s DC Output Drive (high @ VDD/2) IOH 12.5 mA DC Output Drive (low @ VDD/2) IOL 12.5 mA Capacitance of the PAD pin CPIN 1.5 pF Maximum Load @1000Mbps CL 1.5 pF TX Mode Power @800Mbps at runlength=2 P 0.65 mW RX Mode Power @800Mbps at runlength=2 P 0.07 mW Hysteresis (when enabled) 5 10 % of VDD Operational Voltage (Core supply) VDD 0.65 0.725 0.825 V Operational Voltage (IO supply) VDDA 0.65 0.725 0.825 V Operational Temperature TOP -40 25 125 C Total area of macro A 0.0018 sq.mm Dimensions: 32um (X) by 55.52um (Y) Table 1: Operational Specifications