CCSDS turbo decoder

Overview

Key Features

• Log-MAP decoding algorithm for best coding gain
• Optional Cyclic Redundancy Check (CRC)
• On the fly change of block size, code rate, number of iterations.
• Single-chip FPGA Core, no external memory required
• Latency reduction by bank-swapping (2 input buffers)
• Encoder available

Applications

• CCSDS

Technical Specifications